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Title: A High Speed Low Power Encoder for a 5 Bit Flash ADC
Authors: Varghese, G T
Mahapatra, K K
Keywords: Analog to digital converter
Flash ADC
Pseudo NMOS logic
Pseudo Dynamic CMOS logic
Issue Date: Dec-2012
Citation: International Conference on green technologies on Mar Baselios college of Engineering and technology, Thiruvananthapuram, Kerala during 18th to 20th Dec, 2012
Abstract: The present investigation proposes an efficient low power encoding scheme intended for a 5GS/s 5 bit flash analog to digital converter. The designing of a thermometer code to binary code is one of the challenging issues in the design of a high speed low power flash ADC. An encoder circuit in this paper translates the thermometer code into the intermediate gray code to reduce the effects of bubble errors. To maintain the high speed with low power dissipation, the implementation of the encoder through pseudo NMOS logic is presented. The proposed encoder is designed using 90nm technology in 1.2 V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 5GHz and the average power dissipation of the encoder is 0.3149 mW which is very less in comparison with current mode logic encoder implementation.
Description: Copyright for this paper belongs to proceeding publisher
Appears in Collections:Conference Papers

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