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Title: Design and Implementation of FPGA based Linear All Digital Phase-Locked Loop
Authors: Das, A
Dash, S
Sahoo, A K
Chitti Babu, B
Keywords: Phase detector
Hilbert Transform
CORDIC algorithm
Phase locked loop
Signal processing
FPGA Implementation
Issue Date: Dec-2012
Citation: IEEE INDICON 2012, International Conference,Cochin, 07-09, December 2012
Abstract: This paper presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a.
Description: Copyright for this paper belongs to proceeding publisher
Appears in Collections:Conference Papers

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