DSpace@nitr >
National Institue of Technology- Rourkela >
Conference Papers >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1736

Full metadata record

DC FieldValueLanguage
contributor.authorVarghese, G T-
contributor.authorMahapatra, K K-
date.accessioned2012-08-08T09:43:13Z-
date.available2012-08-08T09:43:13Z-
date.issued2012-07-
identifier.citation3rd International Conference on computing communication and networking technologies on SNS college of Engineering, Coimbatore during 26th to 28th July, 2012en
identifier.urihttp://hdl.handle.net/2080/1736-
descriptionCopyright belongs to proceeding publisheren
description.abstractThe present investigation proposes an efficient high speed encoding scheme intended for a 5GS/s 5 bit flash analog to digital converter. The designing of a thermometer code to binary code is one of the challenging issues in the design of a high speed flash ADC. An encoder circuit in this paper translates the ther-mometer code into the intermediate gray code to reduce the ef-fects of bubble errors. To increase the speed of the encoder, the implementation of the encoder through pseudo dynamic CMOS logic is presented. The proposed encoder is designed using 90nm technology at 1.2V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 5GHz and the average power dissipation of the encoder is 1.919mW.en
format.extent392027 bytes-
format.mimetypeapplication/pdf-
language.isoen-
subjectAnalog to digital converteren
subjectFlash ADCen
subjectPseudo dynamic CMOS logicen
titleA High Speed Encoder for a 5GS/s 5 Bit Flash ADCen
typeArticleen
Appears in Collections:Conference Papers

Files in This Item:

File Description SizeFormat
Camera Ready paper.pdf382KbAdobe PDFView/Open

Show simple item record

All items in DSpace are protected by copyright, with all rights reserved.

 

Powered by DSpace Feedback