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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1517

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contributor.authorMeher, P-
contributor.authorMahapatra, K K-
date.accessioned2011-08-02T09:12:03Z-
date.available2011-08-02T09:12:03Z-
date.issued2011-06-
identifier.citationInternational Conference on Advanced Computing, Communication and Networks [ICACCN-11], 2-3 June, Hotel Aroma, Chandigarhen
identifier.urihttp://hdl.handle.net/2080/1517-
descriptionCopyright belongs to proceeding publisheren
description.abstractDynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipation with almost same noise immunity compared to the recently proposed circuit techniques for dynamic logic styles to improve noise immunity. The concept is validated through extensive simulation.en
format.extent93102 bytes-
format.mimetypeapplication/pdf-
language.isoen-
subjectDomino logicen
subjectdynamic logicen
subjectpower consumptionen
subjectleakage toleranceen
subjectrobustnessen
titleA Low-Power Circuit Technique for Dynamic CMOS Logicen
typeArticleen
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