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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1421

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contributor.authorSharma, V K-
contributor.authorMahapatra, K K-
contributor.authorPati, U C-
identifier.citationInternational Conference on Devices and Communications, February 24-25, 2011, Birla Institute of Technology, Mesra, Indiaen
descriptionCopyright belongs to Proceedings Publisheren
description.abstractDiscrete cosine transform (DCT) is widely used in image and video compression standards. This paper presents distributed arithmetic (DA) based VLSI architecture of DCT for low hardware circuit cost as well as low power consumption. Low hardware cost is achieved by exploiting redundant computational units in recent literature. A technique to reduce error introduced by sign extension is also presented. The proposed 1-D DCT architecture is implemented in both the Xilinx FPGA and Synopsys DC using TSMC CLN65GPLUS 65nm technology library. For power and hardware cost comparisons, recent DA based DCT architecture is also implemented. The comparison results indicate the considerable power as well as hardware savings in presented architecture. 2-D DCT is implemented using row column decomposition by the proposed 1-D DCT architecture.en
format.extent212850 bytes-
subject2-D Discrete cosine transform (DCT)en
subjectDistributed Arithmetic (DA)en
subjectImage compression,en
titleAn Efficient Distributed Arithmetic based VLSI Architecture for DCTen
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