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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1349

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contributor.authorMukherjee, S-
contributor.authorSahoo, Bibhudatta-
date.accessioned2011-01-17T09:17:53Z-
date.available2011-01-17T09:17:53Z-
date.issued2011-
identifier.citationProceeding of International Conference on Electronic Systems (ICES-2011), page 383 – 389, Excel India Publishers, New Delhi, 2011en
identifier.isbn978-93-80697-50-5-
identifier.urihttp://hdl.handle.net/2080/1349-
descriptionCopyright belongs to Proceedings Publisheren
description.abstractThis paper covers the implementation of the International Data Encryption Algorithm (IDEA) using Very Large Scale Integrated Circuits Hardware Description Language (VHDL) with the help of Xilinx – ISE 10.1. In terms of security, this algorithm is very much superior and is already patented by Ascom. The whole algorithm is divided into modules and among all of them the most time consuming one is the modulo multiplication module. The multiplication algorithm that is used computes the product in a recursive fashion and it uses Divide and Conquer approach during multiplication, as mentioned in [2], which ultimately consumes less time and increases the throughput in the algorithm. Moreover the design is made pipelined for increasing the throughput. The block size considered here is same as of traditional IDEA encryption algorithm [1] which is of 64 bits with 16 bit sub-blocks [1].en
format.extent161280 bytes-
format.mimetypeapplication/pdf-
language.isoen-
publisherExcel India Publishersen
subjectCryptographicAlgorithmen
subjectIDEAen
subjectHardware Implementationsen
subjectModulo Multiplieren
subjectVHDLen
subjectPartial Productsen
titleA Hardware implementation of IDEA cryptosystem using a recursive multiplication approachen
typeArticleen
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