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Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1323

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contributor.authorSharma, V K-
contributor.authorPati, U C-
contributor.authorMahapatra, K K-
date.accessioned2010-12-09T06:23:30Z-
date.available2010-12-09T06:23:30Z-
date.issued2010-12-
identifier.citationInternational Conference on Power, Control & Embedded Systems (ICPCES 2010), November 28- December 01, 2010en
identifier.urihttp://hdl.handle.net/2080/1323-
descriptionCopyright belongs to the Proceeding of Publisheren
description.abstractAs the circuit complexity is increasing in demand for the more computations on a single VLSI chip, low power VLSI design has become important specially for portable devices powered by battery. Digital camera is one of them where real-time image capturing, compression and storage of compressed image data is done. Most of the digital camera implement JPEG baseline algorithm to store highly compressed image in camera memory. In this paper we report and present low cost, low power and computationally efficient circuit design of JPEG for digital camera to get highly compressed image by exploiting removal of subjective redundancy from the image.en
format.extent728920 bytes-
format.mimetypeapplication/pdf-
language.isoen-
subjectDiscrete cosine transform (DCT)en
subjectImage compressionen
subjectJPEGen
subjectQuantization matrixen
subjectSubjective redundancyen
titleAn Study of Removal of Subjective Redundancy in JPEG for Low Cost, Low Power, Computation efficient Circuit Design and High Compression Imageen
typeArticleen
Appears in Collections:Conference Papers

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