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|dc.contributor.author||Mahapatra, K K||-|
|dc.identifier.citation||National Conference on Wireless Communication and VLSI Design, March, 27-28, Gwalior, India||en|
|dc.description.abstract||Usually there are two approaches to design an application specific instruction set processor (ASIP). One of them is at Register Transfer Level (RTL) and another is at just higher level than RTL. Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. It comprises several stages to design a processor using ADLs. These are architecture design implementation, software development, instruction and system verification. Verification of such ASIPs at various design stages is a tedious job to do. This paper presents the architecture description of a FIR filter using ADL based instruction set description. Here the design process is more consistent while allowing maximum flexibility. Furthermore, it enables the design process in both instruction and cycle accurate modes. The design process of a FIR filter with pipelining is demonstrated here. The main advantage is that the FIR filter model can be optimized with respect to resources by changing the LISA code written in Coware platform.||en|
|dc.title||Design of a Pipelined FIR Filter Using Application Description Language||en|
|Appears in Collections:||Conference Papers|
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