An Explainable Multi-Stage RTL Hardware Trojan Detection Framework Using Structural, Semantic, and Risk-Aware Analysis

Abstract

Hardware Trojans (HTs) pose a grave danger to the safety and performance of integrated circuits (ICs). Such modifications may occur at any phase of the hardware design and manufacturing process. Detecting HTs at the RTL stage is difficult because they operate only under specific conditions and have a negligible hardware footprint. This work proposes a static HT detection scheme operating at the RTL level, leveraging structural analysis, semantic analysis, and explainable anomaly detection to detect HTs early. The proposed method comprises three steps. In the first step, a low-cost RTL scanner detects suspicious coding and abnormal RTL constructs. In the second step, a golden reference-based analysis is conducted on both the trusted design and the target RTL design to identify any differences in their structure and semantics. Finally, the PEARL explainable anomaly detection scheme is utilized to generate anomaly and malicious scores. The proposed framework has been tested using Trust-Hub benchmark based RTL designs across three scenarios. The experimental analysis has shown that the PEARL explainable anomaly detection framework achieves 95.52% accuracy (A), 99.5% precision (P), 91.67% recall(R), and an F1 score of 95.65%. Based on the results, the proposed multistage detection framework is highly promising and can effectively detect hardware Trojans.