FPGA-Based Hardware Implementation of Image Filtering Techniques for Noisy Image Restoration

Abstract

This paper proposes an implementation of image filtering algorithms using FPGAs for restoring noisy images. The implementation is on the Basys-3 FPGA platform, using Verilog HDL and Xilinx Vivado. The implementation is based on a modular structure, including block RAM for image stor-age, filtering blocks, and a VGA controller for image display. The images are converted to a 96-bit COE format, enabling filtering with a 3x3 neighbourhood. The implementation also uses a control block, enabling switching between filters for real-time observation of filtered images. The implementation uses mean, median, Gaussian, Kalman, and colour-intensity filters. The median filter effectively removes salt and pepper noise while preserving edge details. The Gaussian filter is effectively smoothing images when Gaussian noise is present. The imple-mentation also uses an approximate multiplier for arithmetic operations and an adaptive Kalman filter for effective noise reduction without additional hardware. The implementation is effective for frame-by-frame processing at VGA rates, enabling real-time applications. The implementation is useful in various applications, including surveillance, navigation, and biomedical imaging.