Power-Delay Optimized Composite Field AES S-box/ S-1-box using Parallel Processing and Retiming for Secure Industrial IoT Applications

Abstract

The Industrial Internet of Things (IIoT) environment requires lightweight and highly secure cryptographic primitives to protect sensitive industrial data against emerging cyberattacks. The Advanced Encryption Standard (AES) is a widely used symmetric encryption. Nevertheless, the Substitution Box (S-box) is the most hardware-intensive component, occupying the largest area in AES hardware implementations while also consuming significant power and introducing high latency. Furthermore, the existing S-box designs fail achieve a better trade-off between power and delay without increasing circuit complexity. This paper proposes an AES 8-bit S-box and Inverse S-box (S-1-box) architectures with low power and operating on a hierarchical subfield decomposition GF(((2)2)2 to mitigate these limitations. Furthermore, parallel computation of determinants, shared XOR logic, and retiming pipelining are used in the proposed architecture to minimize the depth of the logic and critical path delay. The synthesis results indicate that the proposed architecture provides an average delay and power reduction of 8.4% and 1.5%, respectively, along with Power-Delay Product (PDP) improvement of 4.5% compared with existing literature. Similarly, the proposed S-1-box achieves 12.9% and 6.9% delay and power reduction, respectively, with a 14.7% PDP improvement. Moreover, the proposed design provides a reasonable trade-off between power and delay without increasing the area.