Bitstream-Level Hardware Trojan Detection in FPGAs using Compression and Complexity Analysis

Abstract

Hardware Trojans pose a serious security threat to FPGA-based systems, as they can be deeply embedded within hardware designs. And difficult to detect using conventional testing techniques, particularly when design-level information is unavailable. This paper presents a bitstream-level framework for detecting hardware Trojans in FPGA designs without requiring access to RTL source code or internal design knowledge. FPGA configuration bitstreams from clean and Trojan-inserted circuits are converted into binary sequences and analyzed using a sliding-window approach for localized inspection. The complex or structural irregularities caused by addition of Trojan design logic to circuits are evaluated by calculating normalized Lempel-Ziv complexity for each window and using GZIP based compression measurements to identify how much redundancy changes oc-curred in the bitstream. The evaluation of these systems include the use of MAD based adaptive thresholding to robustly identify trojan impacted regions from normal design variabilities. Experi-mental evaluation of the proposed framework through Trust-Hub FPGA benchmark systems indicates that it can effectively detect stealthy and dormant trojans allowing identification of trojan impacted regions within FPGA configuration bitstreams.