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http://hdl.handle.net/2080/823
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DC Field | Value | Language |
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dc.contributor.author | Das, J K | - |
dc.contributor.author | Mahapatra, K K | - |
dc.date.accessioned | 2009-05-18T06:00:57Z | - |
dc.date.available | 2009-05-18T06:00:57Z | - |
dc.date.issued | 2008 | - |
dc.identifier.citation | International Conference on Electronic Design, ICED, Penang December 1-3,2008. | en |
dc.identifier.uri | http://dx.doi.org/10.1109/ICED.2008.4786698 | - |
dc.identifier.uri | http://hdl.handle.net/2080/823 | - |
dc.description.abstract | In the present investigation, a low power FIR filter using FDF structure is designed which is a key component in a hearing aid application. The details of design are presented. A novel low power latch using 10 transistors is pro-posed that uses dual edge triggering. It is shown a power saving up to 65% is achieved in the FIR filter using the proposed latch. This filter will find application in a hearing aid, which demands area/power constraint and would be useful for other DSP based portable devices. | en |
dc.format.extent | 981651 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | - |
dc.publisher | IEEE | en |
dc.subject | FIR filters | en |
dc.subject | flip-flops | en |
dc.subject | hearing aids | en |
dc.subject | low-power electronics | en |
dc.title | Low Power Filter Design using a Novel Dual Edge Triggered Latch | en |
dc.type | Article | en |
Appears in Collections: | Conference Papers |
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