Asynchronous FIFO in FPGA for Video Acquisition in IoT-Based Systems

Abstract

High-speed video acquisition over Ethernet on FPGA platforms presents significant challenges due to strict real-time bandwidth requirements and susceptibility to packet jitter and synchronization errors. Asynchronous FIFO buffers play a critical role in such systems by decoupling write and read clock domains, thereby ensuring continuous and reliable data flow. This paper presents a custom dual-clock FIFO architecture for real-time video acquisition in IoT-based FPGA systems. Ethernet payloads arriving at 125 MHz are decoded into a 32-bit RGB stream and written into the FIFO, while data are read at 175 MHz for downstream processing. A FIFO depth of 4 KB is selected to buffer one video line, effectively absorbing jitter and mitigating packet delay variations. The design is implemented in Verilog HDL and verified using AMD Vivado 2024.1 under worst-case burst conditions. The simulation results demonstrate stable clock-domain crossing, correct RGB reconstruction, and zero frame loss. A quantitative comparison with the IP of the Vivado FIFO Generator confirms identical throughput. The proposed FIFO architecture provides improved design transparency and configurability, making it well suited for reliable, real-time FPGA-based video acquisition pipelines.