Fault Resilience in Memristor Crossbar: Sensitivity-Driven Mapping for Neural Accelerators

Abstract

The ability of resistive memory (ReRAM) to inherently perform vector-matrix multiplication (VMM), the core operation in the training and inference phase of neural networks, has drawn significant attention from researchers. Download-and-execute schemes are typically employed for ReRAM crossbars, where network weights are trained on a host system and subsequently programmed onto the crossbar. However, defective memristors and inter-device discrepancies frequently prevent cells from accurately storing the learned values, leading to considerable accuracy degradation during inference. This work proposes a fault-aware critical-subset mapping framework to address this issue. Our methodology initially trains the network with hardware variability awareness, considering non-ideal device impacts to enhance robustness. During deployment, only the top-k% most sensitive rows and columns of the weight matrices, determined via sensitivity analysis, are selected for program-verify iterations. In this subgroup, fault-aware placement prioritizes the allocation of substantial weights to appropriate devices, thereby reducing the impact of faults and variations. Experiments indicate that this method maintains over 92% accuracy with up to 10% defective cells for the MNIST dataset, showcasing a scalable and cost-effective mapping strategy.