Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/4646
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dc.contributor.authorHussain, Faeq-
dc.contributor.authorSarkar, Santanu-
dc.date.accessioned2024-08-13T11:15:41Z-
dc.date.available2024-08-13T11:15:41Z-
dc.date.issued2024-04-
dc.identifier.citation9th International Conference on Convergence of Technology (I2CT), Pune, India, 5-7 April 2024en_US
dc.identifier.urihttp://hdl.handle.net/2080/4646-
dc.descriptionCopyright of this document belongs to proceedings publisher.en_US
dc.description.abstractThis paper describes the design and implementation of RISC-V 5-Stage pipelined processor on Basys-3 FPGA Board. The RISC-V core is based on RV32I instruction set architecture. The five-stages of pipelines are namely, instruction fetch, instruction decode, execute, memory access and write back stages with a hazard control unit which contains a stall controller. The proposed RISC-V processor is designed with a Harvard storage structure. RISC-V processor was pipelined to increase the throughput and the maximum operating frequency. For single cycle RISC-V processor maximum 31.6MHz operating frequency is achieved. The five-stage pipelined RISCV processor is implemented on the Basys-3 board at a clock frequency of 50MHz and it had worst net slack (WNS) of 8.6ns which indicates that the maximum operating frequency can be 87.86MHz and nearly 2.78 times the maximum frequency of the single cycle prpcessor. The power consumption also improved from 244mW to 96mWen_US
dc.subjectRISC-Ven_US
dc.subjectFPGAen_US
dc.subjectRISCen_US
dc.subjectRV32I ISAen_US
dc.subjectPipelineden_US
dc.titleDesign and FPGA Implementation of Five Stage Pipelined RISC -V Processoren_US
dc.typeArticleen_US
Appears in Collections:Conference Papers

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