Please use this identifier to cite or link to this item:
http://hdl.handle.net/2080/4646
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hussain, Faeq | - |
dc.contributor.author | Sarkar, Santanu | - |
dc.date.accessioned | 2024-08-13T11:15:41Z | - |
dc.date.available | 2024-08-13T11:15:41Z | - |
dc.date.issued | 2024-04 | - |
dc.identifier.citation | 9th International Conference on Convergence of Technology (I2CT), Pune, India, 5-7 April 2024 | en_US |
dc.identifier.uri | http://hdl.handle.net/2080/4646 | - |
dc.description | Copyright of this document belongs to proceedings publisher. | en_US |
dc.description.abstract | This paper describes the design and implementation of RISC-V 5-Stage pipelined processor on Basys-3 FPGA Board. The RISC-V core is based on RV32I instruction set architecture. The five-stages of pipelines are namely, instruction fetch, instruction decode, execute, memory access and write back stages with a hazard control unit which contains a stall controller. The proposed RISC-V processor is designed with a Harvard storage structure. RISC-V processor was pipelined to increase the throughput and the maximum operating frequency. For single cycle RISC-V processor maximum 31.6MHz operating frequency is achieved. The five-stage pipelined RISCV processor is implemented on the Basys-3 board at a clock frequency of 50MHz and it had worst net slack (WNS) of 8.6ns which indicates that the maximum operating frequency can be 87.86MHz and nearly 2.78 times the maximum frequency of the single cycle prpcessor. The power consumption also improved from 244mW to 96mW | en_US |
dc.subject | RISC-V | en_US |
dc.subject | FPGA | en_US |
dc.subject | RISC | en_US |
dc.subject | RV32I ISA | en_US |
dc.subject | Pipelined | en_US |
dc.title | Design and FPGA Implementation of Five Stage Pipelined RISC -V Processor | en_US |
dc.type | Article | en_US |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
2024_I2CT_FHussain_Design.pdf | 723.38 kB | Adobe PDF | View/Open Request a copy |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.