Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/4639
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dc.contributor.authorVerma, Vishal Kumar-
dc.contributor.authorMukherjee, Atin-
dc.date.accessioned2024-08-07T04:50:03Z-
dc.date.available2024-08-07T04:50:03Z-
dc.date.issued2024-07-
dc.identifier.citationIEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), IISc, Bangalor, 12-14 July 2024en_US
dc.identifier.urihttp://hdl.handle.net/2080/4639-
dc.descriptionCopyright belongs to proceeding publisheren_US
dc.description.abstractA multiplier is a major component in digital signal processors (DSP) for performing fast Fourier transform (FFT) and filtering. In this paper, a multi-bit fault tolerant array multiplier has been designed that provides resiliency against various issues that can lead to faults in the system. To design it, we have only used spare adders and multiplexers along with the simple array multiplier. The design incorporates dynamic hardware redundancy, utilizing spare modules to enhance fault detection and tolerance capabilities. Our analysis indicates that the proposed fault tolerant multiplier can effectively tolerate upto three faults simultaneously, thus significantly enhancing the reliability. Our proposed multiplier also offers 40% savings in the area, 45% reduction in power consumption and 18% less delay overhead when compared to the existing fault tolerant multiplier. However, the proposed multiplier is not fully scalable for higher order designs and hardware complexity also increases with the size of the multiplieren_US
dc.subjectarray multiplieren_US
dc.subjectiterative logic array (ILA)en_US
dc.subjectdynamic reconfigurationen_US
dc.subjectstuck-at-faulten_US
dc.subjectbridging faulten_US
dc.subjecttriple modular redundancy (TMR)en_US
dc.titleDesign of Multi-bit Fault Tolerant Array Multiplieren_US
dc.typeArticleen_US
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