Design of Multi-bit Fault Tolerant Array Multiplier

Abstract

A multiplier is a major component in digital signal processors (DSP) for performing fast Fourier transform (FFT) and filtering. In this paper, a multi-bit fault tolerant array multiplier has been designed that provides resiliency against various issues that can lead to faults in the system. To design it, we have only used spare adders and multiplexers along with the simple array multiplier. The design incorporates dynamic hardware redundancy, utilizing spare modules to enhance fault detection and tolerance capabilities. Our analysis indicates that the proposed fault tolerant multiplier can effectively tolerate upto three faults simultaneously, thus significantly enhancing the reliability. Our proposed multiplier also offers 40% savings in the area, 45% reduction in power consumption and 18% less delay overhead when compared to the existing fault tolerant multiplier. However, the proposed multiplier is not fully scalable for higher order designs and hardware complexity also increases with the size of the multiplier