Optimized Composite Field Based Hardware Architectures for AES S-box using Logic Decomposition Techniques

Abstract

This paper proposes optimized architectures for AES substitution boxes using functional decomposition techniques. Functional decomposition techniques are logic synthesis approaches useful in reducing the support size of complex Boolean functions with more literals. The functional decomposition techniques in this work are applied to the multiplicative inverse function of the AES S-box constructed using sub-field arithmetic based on a normal basis. Three architectures are proposed; the first is based on single-variable decomposition, while the second and third are based on double-variable decomposition techniques. The proposed architectures exhibit high throughput and less area than AES’s existing architectures. It is observed that the best of our proposed designs has a reduction of around 18% in the number of slices and nearly 50% in power consumption compared with the state-of-the-art architectures for the FPGA platform. Again, for standard cell libraries, our proposed design exhibits a delay reduction of around 41%, making them useful for resource-constrained applications.