Novel Four-Stage Comparator With High Speed and Low Kickback Noise

Abstract

The implementation of CMOS four-stage comparator with improved speed, kickback noise and resolution is the subject of this paper. After performing functional verification, it is observed that cascading of pre-amplifiers can achieve a faster speed, the proposed comparator offers higher speed of operation, as compared to typical dynamic comparators referred in this paper. Furthermore, the noise cancelling mechanism of a complementary input pair is used at the preamplifier stage in the proposed four-stage comparator, which is identicalto that of the referred three-stage comparator. The kickbacknoise is considerably reduced compared to that in the three stage comparator by introducing a new method for kickback noise cancellation which will stabilize the operating point. The proposed comparator also offers a better resolution compared to the stateof-the-art work, during the regeneration stage, itsignificantly helpsto boostthe speed even more. Simulated results show that the proposed four-stage comparator reduces the delay and kickback noise by 45.53 % and 32.35 % respectively as compared to Zhuang’s Comparator. All simulations are run on the same technology node TSMC 180nm for fair comparison with the existing designs. These advantages are obtained at the cost of increased energy per comparison and input referred noise marginally.