VLSI Architecture Design of Motion Estimation Block with Hexagon-Diamond Search Pattern for Real-Time Video Processing

Abstract

In recent times, design of efficient video encoders is very important because of their ubiquitous use in mobile and small hand-held battery operated portable devices. Block based motion estimation algorithm is known to be the best and the simplest among various motion estimation techniques, whereas hexagon-diamond search (HEXDS) block matching algorithm is the most efficient block matching algorithms, due to its fewer number of computations and higher speed of searching. This method is equally important for the recently prevailing High Efficiency Video Coding (HEVC) standard for video compression along with the existing Advanced Video Coding (AVC) standard. In this paper, an architecture for the motion estimation block has been proposed along with the address generation for HEXDS algorithm. The architecture achieves maximum frequency of 200 MHz and have a gate count of 12.6k, while implemented in Verilog HDL and mapped to Virtex-4 FPGA.