Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/3561
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dc.contributor.authorMukherjee, Atin-
dc.date.accessioned2021-01-21T05:37:40Z-
dc.date.available2021-01-21T05:37:40Z-
dc.date.issued2020-11-16-
dc.identifier.citation2020 IEEE REGION 10 CONFERENCE (TENCON)Osaka, Japan, November 16-19, 2020en_US
dc.identifier.urihttp://hdl.handle.net/2080/3561-
dc.descriptionCopyright of this paper is with proceedings publisheren_US
dc.description.abstractIn this paper, we have proposed a new fault tolerant design technique for majority voter that is used in selection of final output for fault-tolerant methods like N-tuple modular redundancy (NMR) and N-tuple interwoven redundancy (NIR). The common assumption that majority voters are robust and hence does not affect the final reliability of a system, is false for most of the practical applications. We have used redundancy at transistor level combined with redundancy at gate level to design a defect tolerant majority voter that provides notable improvement in reliability over conventional triple modular redundancy technique using traditional non-reliable voters and other existing methodsen_US
dc.subjectfault toleranceen_US
dc.subjecttriple modular redundancyen_US
dc.subjectmajority voteren_US
dc.subjectreliabilityen_US
dc.subjectquadded transistor logicen_US
dc.titleDefect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logicen_US
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