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http://hdl.handle.net/2080/3561
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DC Field | Value | Language |
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dc.contributor.author | Mukherjee, Atin | - |
dc.date.accessioned | 2021-01-21T05:37:40Z | - |
dc.date.available | 2021-01-21T05:37:40Z | - |
dc.date.issued | 2020-11-16 | - |
dc.identifier.citation | 2020 IEEE REGION 10 CONFERENCE (TENCON)Osaka, Japan, November 16-19, 2020 | en_US |
dc.identifier.uri | http://hdl.handle.net/2080/3561 | - |
dc.description | Copyright of this paper is with proceedings publisher | en_US |
dc.description.abstract | In this paper, we have proposed a new fault tolerant design technique for majority voter that is used in selection of final output for fault-tolerant methods like N-tuple modular redundancy (NMR) and N-tuple interwoven redundancy (NIR). The common assumption that majority voters are robust and hence does not affect the final reliability of a system, is false for most of the practical applications. We have used redundancy at transistor level combined with redundancy at gate level to design a defect tolerant majority voter that provides notable improvement in reliability over conventional triple modular redundancy technique using traditional non-reliable voters and other existing methods | en_US |
dc.subject | fault tolerance | en_US |
dc.subject | triple modular redundancy | en_US |
dc.subject | majority voter | en_US |
dc.subject | reliability | en_US |
dc.subject | quadded transistor logic | en_US |
dc.title | Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic | en_US |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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Atin M (Tencon '20).pdf | 1.19 MB | Adobe PDF | View/Open |
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