Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/3560
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dc.contributor.authorMishra, Ruby-
dc.contributor.authorOkade, Manish-
dc.contributor.authorMahapatra, Kamalakanta-
dc.date.accessioned2021-01-21T05:27:17Z-
dc.date.available2021-01-21T05:27:17Z-
dc.date.issued2020-12-
dc.identifier.citationIEEE-iSES 220, Chennai, India, 14-16Dec2020en_US
dc.identifier.urihttp://hdl.handle.net/2080/3560-
dc.descriptionCopyright of this paper is with proceedings publisheren_US
dc.description.abstractThis paper presents the design of three differenttypes of S-box architectures for the PRESENT cipher with anaim of optimizing the design parameters for resource constrainedapplications. Three variants of S-box design are proposed here.The first includes minimization of the existing Boolean functionusing logic minimization and K-maps, while the other twodesigns focus on MUX-based design optimizations. The proposeddesigns give us an idea about the trade-offs involved in thedesign and performance metrics. FPGA implementations of theproposed design which includes modifying the substitution layer,reduces the slices used by around 27%and also achieves anenhancement of throughput when compared with related state-of-the-art architectures. These results are tailor made to meet thedesign specifications for IoT enabled devices which to the bestof our knowledge has not been investigated earlieren_US
dc.subjectcipheren_US
dc.subjectsubstitution layeren_US
dc.subjectpermutation layeren_US
dc.subjectround keyen_US
dc.subjectIoT applicationsen_US
dc.titleOptimized S-Box Architectures of PRESENTCipher for Resource Constrained Applicationsen_US
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