Optimized S-Box Architectures of PRESENTCipher for Resource Constrained Applications

Abstract

This paper presents the design of three differenttypes of S-box architectures for the PRESENT cipher with anaim of optimizing the design parameters for resource constrainedapplications. Three variants of S-box design are proposed here.The first includes minimization of the existing Boolean functionusing logic minimization and K-maps, while the other twodesigns focus on MUX-based design optimizations. The proposeddesigns give us an idea about the trade-offs involved in thedesign and performance metrics. FPGA implementations of theproposed design which includes modifying the substitution layer,reduces the slices used by around 27%and also achieves anenhancement of throughput when compared with related state-of-the-art architectures. These results are tailor made to meet thedesign specifications for IoT enabled devices which to the bestof our knowledge has not been investigated earlier