Novel Standby Leakage Reduction Technique in SRAM Cell with Enhanced Read Data Stability by Dynamically Varying the Cell Ratio and Pull-up Ratio using Wordline

Abstract

The reliability and toughness of any SRAM cell is tarnished by miniaturization of device technology because of exponential increase in leakage current components in semiconductor devices. This article presents a novel SRAM cell topology to improve the standby leakage power dissipation, by dynamically varying the Cell Ratio and Pull-up ratio using wordline. The entire SRAM cell evaluation is performed at 45nm CMOS Technology. The standby leakage power dissipation of novel design is reduced to 63% as compared to standard six transistor based SRAM cell (6T). The read mode noise margin of novel design becomes 1.056× times than 6T SRAM cell. Further, the effect of process variation also considered for simulation. It also verifies that the novel design offers 8.30nW average (or mean) standby leakage power dissipation as compared to 13.60nW in 6T