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http://hdl.handle.net/2080/3471
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DC Field | Value | Language |
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dc.contributor.author | Samoju, Visweswara Rao | - |
dc.contributor.author | Saramekala, Gopi Krishna | - |
dc.contributor.author | Tiwari, Pramod Kumar | - |
dc.contributor.author | Swain, Ayas Kanta | - |
dc.contributor.author | Mahapatra, Kamalakanta | - |
dc.date.accessioned | 2020-01-16T13:57:46Z | - |
dc.date.available | 2020-01-16T13:57:46Z | - |
dc.date.issued | 2019-12 | - |
dc.identifier.citation | IEEE International Symposium on Smart Electronic Systems(IEEE-iSES), Rourkela, India, 16-18 December 2019 | en_US |
dc.identifier.uri | http://hdl.handle.net/2080/3471 | - |
dc.description | Copyright belongs to proceeding publisher | en_US |
dc.description.abstract | This paper presents analytical modeling and simulation of output current-voltage characteristics, output conductance, and transconductance of dual metal quadruple gate (DMQG) MOSFET. With the help of above said characteristics, this work analyzes the drain current and analog characteristics dependence on device parameters such as gate length ratio and work function ratios. The results of the modeling are compared with those obtained by a 3D ATLAS device simulator to verify the accuracy of the proposed model. Finally, it is observed that the optimum performance of a fixed channel length device is possible with higher control gate length than the screen gate length. | en_US |
dc.subject | Quadruple Gate (QG) | en_US |
dc.subject | Dual Metal (DM) | en_US |
dc.subject | Transconductance (𝒈𝒎) | en_US |
dc.subject | Drain conductance (𝒈𝒅) | en_US |
dc.subject | Control gate | en_US |
dc.subject | Screen gate | en_US |
dc.title | Modeling of Drain Current and Analog Characteristics of Dual-Metal Quadruple Gate (DMQG) MOSFETS | en_US |
dc.type | Article | en_US |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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2019_IEEE-iSES_VRSamoju_Modelling.pdf | 719.64 kB | Adobe PDF | View/Open |
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