An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/3009

Full metadata record

DC Field	Value	Language
dc.contributor.author	Pyne, Sumanta	-
dc.date.accessioned	2018-06-12T12:43:24Z	-
dc.date.available	2018-06-12T12:43:24Z	-
dc.date.issued	2018-05	-
dc.identifier.citation	ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, Illinois, USA, 23-25 May 2018	en_US
dc.identifier.uri	http://hdl.handle.net/2080/3009	-
dc.description	Copyright of this document belongs to proceedings publisher.	en_US
dc.description.abstract	The present work introduces a hardware based technique for reduction of in-rush current in processors with power gating (PG) facility. A PG instruction has been introduced which is responsible in turning on multiple components from sleep to active mode at overlapped time intervals. The supporting hardware for the proposed PG instruction allows overlapped wake-up as long as the resultant in-rush current is tolerable by the system. The efficacy of the proposed method is evaluated on MiBench and MediaBench benchmark programs. The proposed method reduces in-rush current by an average of 35% with average performance loss of 5%.	en_US
dc.subject	Leakage power	en_US
dc.subject	Power gating	en_US
dc.subject	Wakeup	en_US
dc.subject	In-rush current	en_US
dc.subject	Architectural support	en_US
dc.title	An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating	en_US
dc.type	Article	en_US
Appears in Collections:	Conference Papers

Files in This Item:

File	Description	Size	Format
2018_GLSVLSI_SPyne_Architectural.pdf		542.05 kB	Adobe PDF	View/Open