An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating

Abstract

The present work introduces a hardware based technique for reduction of in-rush current in processors with power gating (PG) facility. A PG instruction has been introduced which is responsible in turning on multiple components from sleep to active mode at overlapped time intervals. The supporting hardware for the proposed PG instruction allows overlapped wake-up as long as the resultant in-rush current is tolerable by the system. The efficacy of the proposed method is evaluated on MiBench and MediaBench benchmark programs. The proposed method reduces in-rush current by an average of 35% with average performance loss of 5%.