Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2853
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dc.contributor.authorKumar K, Sudeendra-
dc.contributor.authorSahoo, Sauvagya-
dc.contributor.authorMahapatra, Abhishek-
dc.contributor.authorSwain, Ayas Kanta-
dc.contributor.authorMahapatra, K. K-
dc.date.accessioned2018-01-05T07:01:21Z-
dc.date.available2018-01-05T07:01:21Z-
dc.date.issued2017-12-
dc.identifier.citationIEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS), Bhopal, India, 18 - 20 December, 2017en_US
dc.identifier.urihttp://hdl.handle.net/2080/2853-
dc.descriptionCopyright of this document belongs to proceedings publisher.en_US
dc.description.abstractResearch on Physical Unclonable Functions (PUF) is well established topic in the field of hardware security. PUF is useful in many security applications like IC metering, IP protection and cryptographic key generation. The PUF circuits proposed in the past are dedicated circuits which are extra overhead in terms of area and power. Utilizing the existing circuit structures like microprocessor, power rails, etc to design PUF can be seen in recent literature. In this paper, we propose a PUF topology based on microprocessor and CRP generation method. We present the interim result in terms of hamming distance to prove sufficient randomness in path delays in the hardware multiplier of OpenMSP430 microprocessor which can be exploited to design the PUF. The simulation and statistical analysis technique is also discussed.en_US
dc.subjectPhysical Unclonable functionen_US
dc.subjectMicroprocessoren_US
dc.subjectHardware securityen_US
dc.titleMicroprocessor Based Physical Unclonable Functionen_US
dc.typeArticleen_US
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