Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2770
Full metadata record
DC FieldValueLanguage
dc.contributor.authorTirupathi, Rakesh-
dc.contributor.authorKar, Sougata Kumar-
dc.date.accessioned2017-10-13T04:24:34Z-
dc.date.available2017-10-13T04:24:34Z-
dc.date.issued2017-09-
dc.identifier.citationIEEE International Conference on Power, Control, Signal & Instrumentation Engineering (ICPCSI), Chennai, TN, India, 21 - 22 September, 2017en_US
dc.identifier.isbn978-1-5386-0814-2-
dc.identifier.urihttp://hdl.handle.net/2080/2770-
dc.descriptionCopyright of this document belongs to proceedings publisher.en_US
dc.description.abstractThis paper presents design and analysis of a capacitive sensor interfacing circuit, which detects the physical signal as a change in capacitance and provides voltage output. Theoretical analysis of synchronous chopper modulation and demodulation is carried out and it is shown that how this technique is utilized to remove the low frequency noise and offset voltage introduced by the operational amplifier. The signal conditioning circuit comprises of a buffer, amplifier, demodulator and low pass filter. Detailed analysis of the circuit, considering sinusoidal variation of change in capacitance is presented. Two demodulator circuit topologies are analysed and their merits and demerits are highlighted. The complete circuit is designed and simulated in UMC 180 nm CMOS process technology and the simulation results are presented.en_US
dc.publisherIEEEen_US
dc.subjectCapacitive sensoren_US
dc.subjectSignal conditioningen_US
dc.subjectChopper modulation and demodulationen_US
dc.titleDesign and Analysis of Signal Conditioning Circuit for Capacitive Sensor Interfacingen_US
dc.typeArticleen_US
Appears in Collections:Conference Papers

Files in This Item:
File Description SizeFormat 
2017_ICPCSI_RTitupathi_Design.pdfConference Paper1 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.