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http://hdl.handle.net/2080/2735
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DC Field | Value | Language |
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dc.contributor.author | K, Sudeendra Kumar | - |
dc.contributor.author | Sahoo, Sauvagya | - |
dc.contributor.author | Mahapatra, Abhishek | - |
dc.contributor.author | Swain, Ayas Kanta | - |
dc.contributor.author | Mahapatra, Kamalakanta | - |
dc.date.accessioned | 2017-07-20T07:20:38Z | - |
dc.date.available | 2017-07-20T07:20:38Z | - |
dc.date.issued | 2017-07 | - |
dc.identifier.citation | IEEE Computer Society Annual Symposium on VLSI, July 3-5, 2017, Bochum, Germany | en_US |
dc.identifier.isbn | 9781509067626 | - |
dc.identifier.uri | http://hdl.handle.net/2080/2735 | - |
dc.description | Copyright of the paper belongs to proceedings publishers. | en_US |
dc.description.abstract | PGA based product development companies need third party IP cores to complete the product design time effectively and cost effectively. The one-time payment upfront licensing of IP cores is impractical for FPGA based products, which does not benefit either IP core vendors or product engineering companies. There is a need for good competitive pricing scheme which benefit product development companies and also secure the revenue to IP core vendors. The Pay-per-Device (PPD) pricing model scheme is a suitable pricing scheme. The PPD pricing schemes proposed in the past are complex in terms of communication between different stake holders and inflexible for product development companies to change the FPGA vendor. In this paper, we propose a PPD pricing scheme which overcomes the disadvantages of earlier techniques with better key management and without compromising the security of IP cores. The product development company can change the FPGA vendor at any time in the product life cycle by incorporating the proposed PPD pricing model. The proposed scheme is verified on Xilinx Artix-7 series FPGA. | en_US |
dc.subject | FPGA IP core | en_US |
dc.subject | Hardware Security | en_US |
dc.subject | IP Rights | en_US |
dc.title | A Flexible Pay-per Device Licensing Scheme for FPGA IP Cores | en_US |
dc.type | Article | en_US |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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2017_ISVLSI_SudeendraKK_A Flexible.pdf | 220.65 kB | Adobe PDF | View/Open |
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