Design of Low Power Operational Amplifier and Digital Latch Circuits Using Power Efficient Charge Steering Technique

Abstract

In today’s world power consumption is a burning issue. Research is going on to find out various new power efficient design techniques. Power dissipation could be reduced by transforming continuous-time current-steering circuits into discrete-time charge-steering circuits. Charge steering shows all potential to emerge as an effective technique to reduce power dissipation for high-speed circuits. This technique can be exploited in the design of both analog and semi-analog circuits such as an op-amp, latches and clock-data recovery (CDR) circuits. This paper discusses the design techniques of charge steering circuits like op-amp and latches. Both 1st stage and 2nd stage op-amp circuits and different type of latches in a single stage and cascade forms are designed. The power and performances of the charge steering circuits are also compared with conventional design techniques like current mode logic (CML) circuits to show the improvements. The results show that the op-amp power dissipation is reduced by approximately 87% with better gain. All circuits have been designed using UMC’s 180 nm CMOS technology.