A 6-Bit 500 MSPS Segmented Current Steering DAC with On-Chip High Precision Current Reference

Abstract

This paper describes the design of a 6-bit 500 MS/s segmented current steering digital-to-analog converter (DAC) for telecommunication applications. The DAC is segmented as 4+2, where the 4 MSB bits are implemented in unary and 2 LSB bits are realized in binary architecture. The DAC is biased using an on-chip current reference to minimize the overall deviation in output due to temperature and supply variations. The proposed DAC achieves a maximum DNL and INL of 0.0036 and 0.0023 LSBs, respectively. The DAC operates at 500 MHz sampling frequency. The proposed DAC is implemented in UMC 180 nm CMOS technology and the simulation results are provided.