Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2418
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dc.contributor.authorNayak, D-
dc.contributor.authorAcharya, D P-
dc.contributor.authorMahapatra, K K-
dc.date.accessioned2015-12-31T12:48:25Z-
dc.date.available2015-12-31T12:48:25Z-
dc.date.issued2015-12-
dc.identifier.citation12th Annual IEEE India Conference (INDICON 2015), Jamia Nagar, New Delhi, 17-20 Dec 2015en_US
dc.identifier.urihttp://hdl.handle.net/2080/2418-
dc.descriptionCopyright for this paper belongs to proceeding publisheren_US
dc.description.abstractThe modern high-performance portable communication devices are the key to make the world more inclusive than before. There is a great demand for highperformance SOC inside the high-performance portable devices. According to ITRS and current research, on chip memory technology plays a great role in the SOC performance. Hence enhancing on-chip memory performance will lead to performance enhancement of the device. A novel SRAM cell is designed which reduces the total power consumption by 15.33%. It also increases the write-ability by 63.61% with respect to the conventional 6T-SRAM cell. It blocks the short-circuit current during state transition to reduce the dynamic power consumption. During a write operation, it initiates the feedback loop process for data latching, earlier than the 6T-SRAM cell which increases the write-ability of the proposed cell by a large amount. A thorough analysis about power consumption, writeability and physical layout design of the proposed cell array is carried out and compared with that of a conventional 6T-SRAM cell array.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectShort-circuit currenten_US
dc.subjectLow poweren_US
dc.subjectDynamic poweren_US
dc.subjectN-Curveen_US
dc.subjectSVNMen_US
dc.subjectSINMen_US
dc.subjectSPNMen_US
dc.subjectWTVen_US
dc.subjectWTIen_US
dc.subjectWTPen_US
dc.titlePower Efficient Design of a Novel SRAM Cell with Higher Write Abilityen_US
dc.typeArticleen_US
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