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http://hdl.handle.net/2080/2418
Title: | Power Efficient Design of a Novel SRAM Cell with Higher Write Ability |
Authors: | Nayak, D Acharya, D P Mahapatra, K K |
Keywords: | Short-circuit current Low power Dynamic power N-Curve SVNM SINM SPNM WTV WTI WTP |
Issue Date: | Dec-2015 |
Publisher: | IEEE |
Citation: | 12th Annual IEEE India Conference (INDICON 2015), Jamia Nagar, New Delhi, 17-20 Dec 2015 |
Abstract: | The modern high-performance portable communication devices are the key to make the world more inclusive than before. There is a great demand for highperformance SOC inside the high-performance portable devices. According to ITRS and current research, on chip memory technology plays a great role in the SOC performance. Hence enhancing on-chip memory performance will lead to performance enhancement of the device. A novel SRAM cell is designed which reduces the total power consumption by 15.33%. It also increases the write-ability by 63.61% with respect to the conventional 6T-SRAM cell. It blocks the short-circuit current during state transition to reduce the dynamic power consumption. During a write operation, it initiates the feedback loop process for data latching, earlier than the 6T-SRAM cell which increases the write-ability of the proposed cell by a large amount. A thorough analysis about power consumption, writeability and physical layout design of the proposed cell array is carried out and compared with that of a conventional 6T-SRAM cell array. |
Description: | Copyright for this paper belongs to proceeding publisher |
URI: | http://hdl.handle.net/2080/2418 |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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PowerEffcient_Nayak_2015.pdf | 567.94 kB | Adobe PDF | View/Open |
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