Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2203
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dc.contributor.authorMeher, P-
dc.contributor.authorMahapatra, K K-
dc.date.accessioned2014-11-11T07:03:21Z-
dc.date.available2014-11-11T07:03:21Z-
dc.date.issued2014-10-
dc.identifier.citationTENCON-2014, Bangkok, Thailand, 22-25 October 2014.en
dc.identifier.urihttp://hdl.handle.net/2080/2203-
dc.descriptionCopyright belongs to proceeding publisheren
dc.description.abstractA significant amount of the total power in highly synchronous systems gets dissipated over clock networks. Therefore, low-power clocking schemes would be promising approaches for high performance designs. To reduce the power consumption and delay, a new flip-flop circuit technique has been designed in CMOS domino logic. These flip-flops are a class of dynamic circuit that can be interfaced with both static and dynamic circuits. This flip-flop results in significant energy savings and operates in high speed. Based on simulation results of UMC 180 nm technology and 200 MHz frequency, we have simulated the flip-flop circuit and compared the result with the previous proposed flip-flops simulated with the same environment. The comparison results of the proposed flip-flop with the previous proposed flip-flop shows that the proposed circuit reduces 80% of power consumption and the speed increases to 70-90%.en
dc.format.extent162094 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoen-
dc.subjectFlip-Flopen
dc.subjectCMOSen
dc.subjectDomino logicen
dc.subjectDynamic logicen
dc.subjectLow poweren
dc.subjectPower-delay producten
dc.subjectprocessorsen
dc.titleA Low-Power CMOS Flip-Flop for High Performance Processorsen
dc.typeArticleen
Appears in Collections:Conference Papers

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