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http://hdl.handle.net/2080/2203
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DC Field | Value | Language |
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dc.contributor.author | Meher, P | - |
dc.contributor.author | Mahapatra, K K | - |
dc.date.accessioned | 2014-11-11T07:03:21Z | - |
dc.date.available | 2014-11-11T07:03:21Z | - |
dc.date.issued | 2014-10 | - |
dc.identifier.citation | TENCON-2014, Bangkok, Thailand, 22-25 October 2014. | en |
dc.identifier.uri | http://hdl.handle.net/2080/2203 | - |
dc.description | Copyright belongs to proceeding publisher | en |
dc.description.abstract | A significant amount of the total power in highly synchronous systems gets dissipated over clock networks. Therefore, low-power clocking schemes would be promising approaches for high performance designs. To reduce the power consumption and delay, a new flip-flop circuit technique has been designed in CMOS domino logic. These flip-flops are a class of dynamic circuit that can be interfaced with both static and dynamic circuits. This flip-flop results in significant energy savings and operates in high speed. Based on simulation results of UMC 180 nm technology and 200 MHz frequency, we have simulated the flip-flop circuit and compared the result with the previous proposed flip-flops simulated with the same environment. The comparison results of the proposed flip-flop with the previous proposed flip-flop shows that the proposed circuit reduces 80% of power consumption and the speed increases to 70-90%. | en |
dc.format.extent | 162094 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | - |
dc.subject | Flip-Flop | en |
dc.subject | CMOS | en |
dc.subject | Domino logic | en |
dc.subject | Dynamic logic | en |
dc.subject | Low power | en |
dc.subject | Power-delay product | en |
dc.subject | processors | en |
dc.title | A Low-Power CMOS Flip-Flop for High Performance Processors | en |
dc.type | Article | en |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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TENCON_2014_PAPER.pdf | 158.29 kB | Adobe PDF | View/Open |
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