Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2133
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dc.contributor.authorChandankhede, R D-
dc.contributor.authorAcharya, D P-
dc.contributor.authorPatra, P K-
dc.date.accessioned2014-05-28T10:51:36Z-
dc.date.available2014-05-28T10:51:36Z-
dc.date.issued2014-
dc.identifier.citationIEEE International Conference on Advanced Communication Control and Computing Technologies - ICACCCT May 8-10, 2014.Ramanathapuram, Tamilnadu, India.en
dc.identifier.urihttp://hdl.handle.net/2080/2133-
dc.descriptionCopyright belongs to the Proceeding of Publisheren
dc.description.abstract1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHzen
dc.format.extent749490 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoen-
dc.publisherIEEEen
dc.subjectSense Amplifieren
dc.subjectSRAM architectureen
dc.subjectcurrent controlled SAen
dc.subjectCache memoryen
dc.titleDesign of High Speed Sense Amplifier for SRAMen
dc.typeArticleen
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