Novel Design Technique of Address Decoder for SRAM

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2129

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DC Field	Value	Language
dc.contributor.author	Mishra, A K	-
dc.contributor.author	Acharya, D P	-
dc.contributor.author	Patra, P K	-
dc.date.accessioned	2014-05-28T10:42:29Z	-
dc.date.available	2014-05-28T10:42:29Z	-
dc.date.issued	2014	-
dc.identifier.citation	IEEE International Conference on Advanced Communication Control and Computing Technologies - ICACCCT May 8-10, 2014.Ramanathapuram, Tamilnadu, India.	en
dc.identifier.uri	http://hdl.handle.net/2080/2129	-
dc.description	Copyright belongs to the Proceeding of Publisher	en
dc.description.abstract	Address Decoder is an important digital block in SRAM which takes up to half of the total chip access time and significant part of the total SRAM power in normal read/write cycle. To design address decoder need to consider two objectives, first choosing the optimal circuit technique and second sizing of their transistors. Novel address decoder circuit is presented and analysed in this paper. Address decoder using NAND-NOR alternate stages with predecoder and replica inverter chain circuit is proposed and compared with traditional and universal block architecture, using 90nm CMOS technology. Delay and power dissipation in proposed decoder is 60.49% and 52.54% of traditional and 82.35% and 73.80% of universal block architecture respectively	en
dc.format.extent	659133 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.publisher	IEEE	en
dc.subject	Address Decoder	en
dc.subject	SRAM architecture	en
dc.subject	Cache memory	en
dc.title	Novel Design Technique of Address Decoder for SRAM	en
dc.type	Article	en
Appears in Collections:	Conference Papers

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