Process Corner Variation Aware Design of Low Power Current Starved VCO

Abstract

Conventionally the integrated circuit designer first carries out the design to achieve the required performance specifications and observes the worst case performance through simulations. If the worst case performance falls well inside the acceptable range then that design is designated as a process variation tolerant design. In such case the design is not truly robust against actual process variations. The randomness of process variations is hardly included in the design phase to minimize their effects on the performance of the fabricated chips. In the present work a novel approach is proposed in which minimizes the process corner performance variation (PCPV) so that the performances of the extreme corner case chips are very close the nominal fabrication case. The nominal case design is also subjected to performance optimization along with the process corner variability. Evolutionary algorithm is suitably employed for simultaneous optimization of all the objectives. The proposed design technique is applied to a CSVCO circuit as a case study and the performance improvement results of Cadence simulation are reported.