Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2094
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dc.contributor.authorNayak, D-
dc.contributor.authorAcharya, D P-
dc.contributor.authorRout, P K-
dc.contributor.authorMahapatra, K K-
dc.date.accessioned2014-02-21T04:44:08Z-
dc.date.available2014-02-21T04:44:08Z-
dc.date.issued2014-
dc.identifier.citationInternational Conference on Electronics and Communication System (ICECS-2014), 14 February 2014, Karpagam College of Engineering, Karpagam, Tamilnaduen
dc.identifier.urihttp://hdl.handle.net/2080/2094-
dc.descriptionCopyright belongs to the IEEEen
dc.description.abstractThe high demand of embedding more and more functionality in a single chip has enforced the use of scaling. As scaling drastically reduce the channel length the leakage current also increases significantly which increases the static power dissipation. A novel 8T-SRAM cell (Leakage Current Reduced SRAM cell) is proposed which reduces the leakage power dissipation significantly in comparison to the conventional 6T-SRAM cell. The cell is designed using GPDK-90 nm technology library and simulated under Cadence Virtuoso design environment. The proposed cell uses a lower voltage than Vdd during standby mode which leads to a reduction of leakage current and hence the static power consumption. The lower voltage is generated using an NMOS which creates a threshold voltage drop when transfer a high logic. The power consumption is found to be 25.02 % lesser than that of conventional six transistors SRAM cell .The stability and the write ability are measured using the N-Curve technique.en
dc.format.extent386199 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoen-
dc.publisherIEEEen
dc.subjectLeakage currenten
dc.subjectLeakage poweren
dc.subjectStatic poweren
dc.subjectLow poweren
dc.subjectstabilityen
dc.subjectN-Curveen
dc.subjectSVNMen
dc.subjectSINMen
dc.subjectWTVen
dc.subjectWTIen
dc.titleDesign of Low-Leakage and High Stable Proposed SRAM cell Structureen
dc.typeArticleen
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