Please use this identifier to cite or link to this item:
http://hdl.handle.net/2080/2094
Title: | Design of Low-Leakage and High Stable Proposed SRAM cell Structure |
Authors: | Nayak, D Acharya, D P Rout, P K Mahapatra, K K |
Keywords: | Leakage current Leakage power Static power Low power stability N-Curve SVNM SINM WTV WTI |
Issue Date: | 2014 |
Publisher: | IEEE |
Citation: | International Conference on Electronics and Communication System (ICECS-2014), 14 February 2014, Karpagam College of Engineering, Karpagam, Tamilnadu |
Abstract: | The high demand of embedding more and more functionality in a single chip has enforced the use of scaling. As scaling drastically reduce the channel length the leakage current also increases significantly which increases the static power dissipation. A novel 8T-SRAM cell (Leakage Current Reduced SRAM cell) is proposed which reduces the leakage power dissipation significantly in comparison to the conventional 6T-SRAM cell. The cell is designed using GPDK-90 nm technology library and simulated under Cadence Virtuoso design environment. The proposed cell uses a lower voltage than Vdd during standby mode which leads to a reduction of leakage current and hence the static power consumption. The lower voltage is generated using an NMOS which creates a threshold voltage drop when transfer a high logic. The power consumption is found to be 25.02 % lesser than that of conventional six transistors SRAM cell .The stability and the write ability are measured using the N-Curve technique. |
Description: | Copyright belongs to the IEEE |
URI: | http://hdl.handle.net/2080/2094 |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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Design of Low-Leakage and High Stable.pdf | 377.15 kB | Adobe PDF | View/Open |
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