Performance Evaluation of Multi-core processors with Varied Interconnect Networks

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/2055

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DC Field	Value	Language
dc.contributor.author	Mohanty, R P	-
dc.contributor.author	Turuk, A K	-
dc.contributor.author	Sahoo, Bibhudatta	-
dc.date.accessioned	2014-01-09T04:34:06Z	-
dc.date.available	2014-01-09T04:34:06Z	-
dc.date.issued	2013	-
dc.identifier.citation	2013 Second International Conference on Advanced Computing, Networking and SecurityNITK, Surathkal, Mangalore, Karnataka, India	en
dc.identifier.uri	http://hdl.handle.net/2080/2055	-
dc.description	Copyright belongs to the proceeding publisher	en
dc.description.abstract	Multi-core and heterogeneous processor systems are widely used now a days. Even mobile devices have two or more cores to improve their performance. While these two technologies are widely used, it is not clear which one would perform better and which hardware configuration is optimal for a specific target domain. In this paper, we proposed an interconnect architecture Multi-core processor with Hybrid network(MPHN). The performance of MPHN has been compared with: (i) Multi-core processor with internal network, and (ii) Multi-core processor with Ring network. This architecture substantially minimizes the communication delay in multicore processors.	en
dc.format.extent	184947 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.subject	Multi-core processor	en
dc.subject	interconnect	en
dc.subject	performance analysis	en
dc.subject	impact of cache size	en
dc.title	Performance Evaluation of Multi-core processors with Varied Interconnect Networks	en
dc.type	Article	en
Appears in Collections:	Conference Papers

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