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http://hdl.handle.net/2080/1933| Title: | A Power Improvement Technique for a Differential LNA |
| Authors: | Swamy, M N Acharya, D P |
| Keywords: | Low Noise Amplifier (LNA) CMOS noise figure (NF) Power |
| Issue Date: | Apr-2013 |
| Citation: | 2nd Students' Conference on Engineering and Systems (SCES 2013) April 12-14, 2013,MNNIT Allahabad |
| Abstract: | This work presents the design of an inductively source degenerated CMOS Differential Low Noise Amplifier (LNA) operating at 2 GHz. LNA is designed using UMC 0.18 μm technology and simulated in Cadence Spectre_RF tool to validate its performance. Power constrained methodology is used for the design of CMOS Differential Low Noise Amplifier. At 1.8V supply voltage, the designed LNA consumed 9mA current. The amplifier.... |
| Description: | Copyright belongs to proceeding publisher |
| URI: | http://hdl.handle.net/2080/1933 |
| Appears in Collections: | Conference Papers |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| finalpaper_paper284.pdf | 239.25 kB | Adobe PDF | View/Open |
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