Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1933
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dc.contributor.authorSwamy, M N-
dc.contributor.authorAcharya, D P-
dc.date.accessioned2013-04-22T09:57:24Z-
dc.date.available2013-04-22T09:57:24Z-
dc.date.issued2013-04-
dc.identifier.citation2nd Students' Conference on Engineering and Systems (SCES 2013) April 12-14, 2013,MNNIT Allahabaden
dc.identifier.urihttp://hdl.handle.net/2080/1933-
dc.descriptionCopyright belongs to proceeding publisheren
dc.description.abstractThis work presents the design of an inductively source degenerated CMOS Differential Low Noise Amplifier (LNA) operating at 2 GHz. LNA is designed using UMC 0.18 μm technology and simulated in Cadence Spectre_RF tool to validate its performance. Power constrained methodology is used for the design of CMOS Differential Low Noise Amplifier. At 1.8V supply voltage, the designed LNA consumed 9mA current. The amplifier....en
dc.format.extent244992 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoen-
dc.subjectLow Noise Amplifier (LNA)en
dc.subjectCMOSen
dc.subjectnoise figure (NF)en
dc.subjectPoweren
dc.titleA Power Improvement Technique for a Differential LNAen
dc.typeArticleen
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