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http://hdl.handle.net/2080/1915
Title: | FPGA Implementation of Discrete Fourier Transform Core Using NEDA |
Authors: | Mankar, A N, Prasad Meher, S |
Keywords: | Discrete Fourier Transform (DFT) new distributed arithmetic (NEDA) FPGA DSP |
Issue Date: | Apr-2013 |
Citation: | IEEE International conference on Communication Systems and Network Technologies-2013, 6-8 April 2013, Mir Labs,Gwalior |
Abstract: | Transforms like Discrete Fourier Transform (DFT) are a major block in communication systems such as OFDM, etc. This paper reports architecture of a DFT core using new distributed arithmetic (NEDA) algorithm. The advantage of the proposed architecture is that the entire transform can be implemented using adder/subtractors and shifters only, thus minimising the hardware requirement compared to other architectures. The proposed design is implemented for 16 – bit data path (12 – bit for comparison) considering both integer representation as well as fixed point representation, thus increasing the scope of usage. The proposed design is mapped on to Xilinx XC2VP30-7FF896 FPGA, which is fabricated using 130 nm process technology. The hardware utilization of the proposed design on the mapped FPGA is 295 slices, 478 4-input LUTs and 304 slice flip flops. The maximum on board frequency of operation of the proposed design is 79.339 MHz. The proposed design has 72.27% improvement in area, 10.31% improvement in both maximum clock frequency and throughput when compared to other designs. |
Description: | Copyright for this article belongs to the publisher |
URI: | http://hdl.handle.net/2080/1915 |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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csnt@abhishek.pdf | 233.5 kB | Adobe PDF | View/Open |
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