Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1915
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dc.contributor.authorMankar, A-
dc.contributor.authorN, Prasad-
dc.contributor.authorMeher, S-
dc.date.accessioned2013-04-12T05:40:06Z-
dc.date.available2013-04-12T05:40:06Z-
dc.date.issued2013-04-
dc.identifier.citationIEEE International conference on Communication Systems and Network Technologies-2013, 6-8 April 2013, Mir Labs,Gwalioren
dc.identifier.urihttp://hdl.handle.net/2080/1915-
dc.descriptionCopyright for this article belongs to the publisheren
dc.description.abstractTransforms like Discrete Fourier Transform (DFT) are a major block in communication systems such as OFDM, etc. This paper reports architecture of a DFT core using new distributed arithmetic (NEDA) algorithm. The advantage of the proposed architecture is that the entire transform can be implemented using adder/subtractors and shifters only, thus minimising the hardware requirement compared to other architectures. The proposed design is implemented for 16 – bit data path (12 – bit for comparison) considering both integer representation as well as fixed point representation, thus increasing the scope of usage. The proposed design is mapped on to Xilinx XC2VP30-7FF896 FPGA, which is fabricated using 130 nm process technology. The hardware utilization of the proposed design on the mapped FPGA is 295 slices, 478 4-input LUTs and 304 slice flip flops. The maximum on board frequency of operation of the proposed design is 79.339 MHz. The proposed design has 72.27% improvement in area, 10.31% improvement in both maximum clock frequency and throughput when compared to other designs.en
dc.format.extent239104 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoen-
dc.subjectDiscrete Fourier Transform (DFT)en
dc.subjectnew distributed arithmetic (NEDA)en
dc.subjectFPGAen
dc.subjectDSPen
dc.titleFPGA Implementation of Discrete Fourier Transform Core Using NEDAen
dc.typeArticleen
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