Please use this identifier to cite or link to this item:
http://hdl.handle.net/2080/1854
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DC Field | Value | Language |
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dc.contributor.author | Lavania, Y | - |
dc.contributor.author | Varghese, G T | - |
dc.contributor.author | Mahapatra, K K | - |
dc.date.accessioned | 2013-02-01T04:14:59Z | - |
dc.date.available | 2013-02-01T04:14:59Z | - |
dc.date.issued | 2013-01 | - |
dc.identifier.citation | IEEE EDS & SKP ICEVENT 2013,International conference on Emerging Trends in VLSI, Embedded Systems, Nano Electronics and Telecommunication System, SKP Engg. College, Tiruvannamalai, 07-Jan-2013 to 09-Jan-2013 | en |
dc.identifier.uri | http://hdl.handle.net/2080/1854 | - |
dc.description | Copyright belongs to proceeding publisher | en |
dc.description.abstract | This investigation suggests a low power encoding scheme proposed for 4GS/s 5 bit flash analog to digital convert-er. One of the demanding issues in the design of a low power flash ADC is the design of thermometer code to binary code. An encoder in this paper converts the thermometer code into binary code without any intermediate stage. To decrease the power consumption of the encoder, the implementation is done using dynamic CMOS logic. The proposed encoder is designed using 90 nm technology at 1.2 V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 4GHz and the average power dissipation of the encoder is 1.833 μW. | en |
dc.format.extent | 705693 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language.iso | en | - |
dc.subject | Analog to digital converter | en |
dc.subject | Flash ADC | en |
dc.subject | Dynamic CMOS logic | en |
dc.title | An Ultra Low Power Encoder for 5 Bit Flash ADC | en |
dc.type | Article | en |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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Ultra Low Power.pdf | 689.15 kB | Adobe PDF | View/Open |
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