Analysing the Performance of Multi-core Architecture

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1853

Full metadata record

DC Field	Value	Language
dc.contributor.author	Mohanty, R P	-
dc.contributor.author	Turuk, A K	-
dc.contributor.author	Sahoo, Bibhudatta	-
dc.date.accessioned	2013-01-31T09:30:56Z	-
dc.date.available	2013-01-31T09:30:56Z	-
dc.date.issued	2012	-
dc.identifier.citation	1st International Conference on Computing, Communication and Sensor Networks- CCSN, (2012), vol. 62, PIET, Rourkela, Odisha, pp.258-264, 2012.	en
dc.identifier.uri	http://hdl.handle.net/2080/1853	-
dc.description	Copyright belongs to proceeding publisher	en
dc.description.abstract	The advancement in technology has brought immense amount of changes in the design and productivity of applications designed for being used in the personal computers. By implementing greater number of cores to the same chip also results in facing challenges. In this case the challenge that is being faced is the core to core communication as well as the memory in addition to cache coherence. This paper presents a detailed analysis on performance of FFT a divide and conquer algorithm across with the Multi-core architecture with Internal and external network. The architectures are being defined using memory configuration and context configuration with help of Multi2Sim 3.4 simulator. The performance of these architectures have been simulated with Splash 2 Benchmark.	en
dc.format.extent	161808 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.subject	Multi-core Technology	en
dc.subject	Multi-core Issues	en
dc.subject	SPLASH2 Benchmark	en
dc.subject	performance	en
dc.subject	Multi2Sim simulator	en
dc.title	Analysing the Performance of Multi-core Architecture	en
dc.type	Article	en
Appears in Collections:	Conference Papers

Files in This Item:

File	Description	Size	Format
Multicore_CCSN-2012.pdf		158.02 kB	Adobe PDF	View/Open

Show simple item record