Design and analysis of five port Router for network on chip

Please use this identifier to cite or link to this item: http://hdl.handle.net/2080/1803

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DC Field	Value	Language
dc.contributor.author	S, Swapna	-
dc.contributor.author	Swain, K K	-
dc.contributor.author	Mahapatra, K K	-
dc.date.accessioned	2012-12-24T12:53:34Z	-
dc.date.available	2012-12-24T12:53:34Z	-
dc.date.issued	2012-12	-
dc.identifier.citation	The Asia-Pacific Conference on Post graduate Research in Microelectronics & Electronics (Prime Asia2012), December 5-7,2012 in Hyderabad, India	en
dc.identifier.uri	http://hdl.handle.net/2080/1803	-
dc.description	Copyright belongs to proceeding publisher	en
dc.description.abstract	With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are buffering registers, demultiplexer, First In First Out registers, and schedulers. The scheduler uses the round robin algorithm. The proposed architecture of five port router is simulated in Xilinx ISE 10.1 software. The source code is written in VHDL.	en
dc.format.extent	264164 bytes	-
dc.format.mimetype	application/pdf	-
dc.language.iso	en	-
dc.subject	network on chip	en
dc.subject	router	en
dc.subject	round robin algorithm	en
dc.title	Design and analysis of five port Router for network on chip	en
dc.type	Article	en
Appears in Collections:	Conference Papers

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