Please use this identifier to cite or link to this item:
http://hdl.handle.net/2080/1803
Title: | Design and analysis of five port Router for network on chip |
Authors: | S, Swapna Swain, K K Mahapatra, K K |
Keywords: | network on chip router round robin algorithm |
Issue Date: | Dec-2012 |
Citation: | The Asia-Pacific Conference on Post graduate Research in Microelectronics & Electronics (Prime Asia2012), December 5-7,2012 in Hyderabad, India |
Abstract: | With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are buffering registers, demultiplexer, First In First Out registers, and schedulers. The scheduler uses the round robin algorithm. The proposed architecture of five port router is simulated in Xilinx ISE 10.1 software. The source code is written in VHDL. |
Description: | Copyright belongs to proceeding publisher |
URI: | http://hdl.handle.net/2080/1803 |
Appears in Collections: | Conference Papers |
Files in This Item:
File | Description | Size | Format | |
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noc_paper_final.pdf | 257.97 kB | Adobe PDF | View/Open |
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